A central processing unit (CPU) serving as an arithmetic processing device which is mounted in an information processing apparatus obtains data from an IO device to process the data. In the information processing apparatus, the communication between the CPU and the IO device is generally performed through a device for communication (hereinafter, referred to as a “communication device”). The communication device may specifically be a bridge large scale integrated circuit (LSI) or a switch LSI.
Generally, a plurality of communication devices is provided in the information processing apparatus to perform communications with the IO device. In the information processing apparatus capable of connecting a plurality of IO devices, the communication devices are connected to each other such that a topology of the connection has a tree structure.
Recently, the demand for power saving is strongly required to suppress the power consumption of the information processing apparatus. In accordance with the demand, a power saving function is provided even in a communication device whose power consumption is comparatively low.
For example, in a peripheral component interconnect express (PCIe) standard, a power management feature called an active-state power management (ASPM) is defined and two communication devices which are connected to each other through a link may be shifted to a power saving state in accordance with a status of the link. That is, the ASPM may suppress the power consumption in accordance with the status of the link.
When the communication devices are shifted to the power saving state, a latency of the link is increased. Therefore, the ASPM is not necessarily used for the information processing apparatus which requires high performance. However, in a circumstance where it is required to suppress power consumption, such as a case where power consumption of the information processing apparatus has a maximum amount or approximates a maximum, it is required to suppress the power consumption of the communication device.
Japanese Laid-Open Patent Publication No. 2006-201881 discloses an information processing apparatus having a PCI Express interface which includes a plurality of lanes, including a controller configured to control the PCI Express interface to maintain an operation state of the interface, and a system managing device which obtains and stores the operation state of the PCI Express interface from the controller when an initial process of the information processing apparatus is completed, and, upon receiving a notice of error occurrence, performs a predetermined corresponding process when degeneration of the number of lanes is detected by comparing the stored operation state with the operation state maintained by the controller.
Japanese Laid-Open Patent Publication No. 2009-93636 discloses an information processing apparatus in which two table data structures are used by a firmware in order to adjust an operating parameter of an end point based on the comparison of a total maximum and/or minimum data transfer rate of a PCIe adaptor/end point (hereinafter, referred to as an end point) with a maximum data transfer rate with respect to a front side bus, that is, a bandwidth of the front side bus. A first table data structure includes various combinations of operating parameter settings in order to control bandwidth usage of each end point of a data processing system. A second table data structure includes a list of end points at which the data processing system supports a related minimum data transfer rate and a priority. Further, the second table data structure instructs which end point has an isochronous requirement.
With respect to the operation, mounted equipment sets a threshold value of an error which may occur during a predetermined period. When the error exceeds the threshold value, the equipment inquires a front side bus performance counter in order to determine whether the front side bus operates at its maximum data transfer rate. When the front side bus does not operate at the maximum data transfer rate, the equipment increases a set value of the data transfer rate with respect to the end point which exceeds the threshold value. When the front side bus operates at its maximum data transfer rate, the equipment inquires all the end points to determine which end point is active. Next, the equipment determines whether there is an end point which has a lower priority than that of a complaining end point. Therefore, the equipment decreases an end point having a low priority by one step and increases the complaining end point by one step. When the front side bus operates at its maximum data transfer rate and there is no end point which is active and has a low priority, the equipment separates only the complaining end point.